Apple is probably paying closer to $20k per wafer, including test and packaging. There have been leaks on pricing in the industry, leading edge process is expensive. Even at 50M chips. TSMC is in a position to command a price that pays to build the next gen fab, and there are other customers.

Masks are also a significant expense. N5 is an EUV intensive process with $10..20M per set. They probably run through a new mask set every 50,000 wafers or so, and likely need 2 mask sets to get beyond 10,000 (two days) so they can swap them out for inspection and cleaning. So their mask costs for the 100,000 wafers they need are somewhere above $50M.

It is interesting to compare with a project like Graviton2 on N7, which is more like $12k per wafer including test and packaging and likely 120 chips yielded at 4cm2 each. They probably need 2M chips per generation, and as their design is not nearly as aggressive as the A14, with far fewer different functional blocks and mostly off the shelf IP, they may have done it with as little as $200M of R&D. So they can get a G2 for as low as $200, maybe as much as $300. That makes each core $5 or less. About a third the price of the DRAM they need per core.

I’m surprised by the level of comp, is that correct $300k+? I assume that’s not all salary?

It might be interesting to compare with the math for some of the earlier working bitcoin ASIC miner chips. Those are obviously much, much, simpler, but could represent a realistic low end.

This is why I only do chips with one transistor, but it’s a very expensive transistor.